|Title:||ECE/CS 5710/6710 - Digital VLSI Design -   Fall 2008|
|Instructor:||Ken Stevens, firstname.lastname@example.org, MEB 4506, 585-9176|
|Classes:||Tue 12:25pm - 1:45pm, WEB 1250|
|Office Hours:||by appointment|
|TA:||Anthony Thatcher, email@example.com|
|Text Book 1:||Principles of CMOS VLSI Design: A Systems Perspective By Weste & Harris|
|Text Book 2:||Crafting a Chip: A practical guide to the UofU VLSI CAD Flow, By Erik Brunvand.|
This is an introductory course in VLSI where you will go from the low level physical transistor and mask design of your own cell library, all the way to the design, implementation, and fabrication of a significant digital integrated circuit.
Many aspects of Digital VLSI design will be introduced in order to take this significant and enjoyable design journey. However, note that this is not a course in digital system design or computer architecture. You will already need to know boolean logic and how to design and implement combinational and sequential digital circuits (such as adders and other datapath logic, and finite state machines). The project will also require some knowledge of computer architecture for you to complete a moderately large digital design.
Topics that will be covered in lectures include:
The class will require extensive use of CAD tools. All of the CAD tools required will be available in the CADE lab. Students must have an account that will allow them to use the CADE machines. These tools do not run on MS Windoze. Therefore some familiarity with various versions of Unix (such as Linux or Solaris) and the X window system is required for this course.
The tools will be discussed in class and you will receive the aid of the TA in the labs and project. However, there is no specific lab class that you are required to attend. You can perform the labs and your project at your own convenience, either in the CADE lab at the University, or across the network. Remember that nothing can replace taking the time to read the CAD tool documentation.
Integrated circuit design is mastered only through experience, so this is a hands-on course with lots of labs and project time. The homework, as well as lectures, will be closely tied to the term project, the design of a simple standard cell library and then the use of that library to design a project. The final library and project will be done in teams (preferably made up of 3 to 4 students). The initial design of cells for the project will be done individually. You must complete the design of these cells on time. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be independent and fully your own work.
Fabrication of your final project is possible thanks to the research funding provided through the MOSIS service. Little is more rewarding that creating a functional integrated circuit. Little is more disappointing that spending time on a design only to have in be non-functional. Therefore, careful design practices must be followed if you are to fabricate your chip including sufficient Design-For-Test, validation of your design, and a quality design review. If you do fabricate the chip, you will be required to take ECE/CS 6712 to test and report on the results. 6712 is a fun class and a reward to those who make the effort to fabricate their designs.
Additional Recommended Textbooks:
Logic Effort - designing fast CMOS Circuits, I. Sutherland, B. Sproull, and D. Harris. Academic Press, 1999
Analysis and Design of Digital Integrated Circuits (3rd ed), David Hodges. McGraw Hill, 2004.
The Design and Analysis of VLSI Circuits, Glasser and Doberpuhl. Addison-Wesley, 1985.
Course Mailing Lists:
There are two class mailing lists, firstname.lastname@example.org and email@example.com. The 5710 list will be used to send out important information to everyone in the class. Please use discretion when sending messages to the entire class. Mail sent to teach-5710 just goes to the instructor and TA. This is the preferred method of communicating with the TA and instructor.
The lists were automatically populated with your university mailing address. If you would like to add another e-mail address, you can send a subscribe request by logging on to the UofU sympa mailing list server. Let me know if you would like to remove your university e-mail address in lieu of another preferred address.
|Incomplete Policy:||You can't get an incomplete unless you have a documented medical or legal emergency.|
|Add/Drop Policy:||The strict University policy is applied.|
|Disability:||If you have a condition that merits consideration, you must contact the instructor at the beginning of the course.|
|Labs and Homework||40%|
|Final Design Review||5%|
|Project (design and report)||40%|
The homework will take the form of problem sets, project proposals, and other written work. The Labs will involve using the VLSI CAD tools to design the mask work and layout of cells that will be used in your project. The class project will require the design of a small digital standard cell library that will then be used as a cell library for a moderate sized functional design. Class members will join design teams for the implementation of the design. The design review will consist of a short presentation of the project to the class. The project report will be a paper in conference or journal format.
Those taking the graduate level course will have additional requirements that include a more rigorous project or design flow and the review of two papers relating to VLSI from journals or conferences in the area. These could be related to the project being implemented.
Details on the requirements for your project reports. Please refer to my links for 6712 and 6770 for example reports students have delivered in previous years.
The labs and homework build upon each other during class.
These need to be completed on-time! There is no general provision for late work.
Labs must be tar'ed up and e-mailed to the TA mailing list.
There will be seven labs in this course as follows:
|Sept 4th||Review Quiz
This quiz will help you brush up on your basic skills, and is due in class Sept. 4th.
|Sept 7th||Lab 1
Schematic capture and Verilog simulation.
Reading: Crafting a Chip, Chapters 1 - 4.
|Sept 14th||Lab 2
Layout editing, DRC, LVS, SPICE simulation.
Reading: Crafting a Chip, Chapters 5 & 6.
|Sept 21st||Lab 3
Flip-Flop and register design.
Reading: Crafting a Chip, Chapters 3 - 6.
Reading: Principles of CMOS VLSI Design, Chapters 1 & 7.
|Sept 28th||Lab 4
Transistor operation, DC simulation.
Reading: Crafting a Chip, Chapter 6.
Reading: Principles of CMOS VLSI Design, Chapter 1, 2 & 4.
Assignment: Textbook problems due Thu Sept. 25th in class
Assignment: Form groups for future assignments, due Thu Sept. 25th in class
|Oct 8th||Lab 5
Five cell library. This is a group lab!
Reading: Crafting a Chip, Chapters 7 & 8.
|Oct 26th||Lab 6
Cell characterization, additional library cells (group lab).
Reading: Crafting a Chip, Chapters 5, 7 & 9.
|Nov 2nd||Lab 7
Cell drive strengths, Place & route, and CPU synthesis (group lab).
Reading: Crafting a Chip, Chapters 7 & 8.
Reading: Principles of CMOS VLSI Design, Chapters 3 - 5.
|Nov 4th||Team Project Proposal
|Dec 11th||Team Project Presentation in class
|Dec 12-22||Schedule Design Review with Instructor
|Dec 19th||Completed Design Due
Paper Review Due (6710 Section Students)
Team Member Peer Evaluation Due
Final Team Project Report Due
|Jan 14th||Design and GDS Stream Due for chips to be fabbed
Following are the team assignments for team lab assignments and class meetings and presentations:
|Team 1||12:25 - 12:38||Chris Chadwick, Ahmed Ragab, Michael Stevens|
|Team 2||12:38 - 12:51||Bernard Chong, Jinpeng Lv, Kyung Jin Park, Xianzong Xie|
|Team 3||12:51 - 1:04||Sandeep Chalasani, Abhishek Mathur, Sri Ramya Venumbaka|
|Team 4||1:04 - 1:17||Arun Jayachandran, Bryson Kent, Samer Merchant, Jonathan Morgan|
|Team 5||1:17 - 1:30||Srinivas Chirla, Shomit Das, Krishnaji Desai, Raghu Gudla, Eliyah Kilada|
|Team 6||1:30 - 1:43||Brandt Hammer, Ben Meakin, Robert Parry, Paul Pryor, Andrew Tolboe|
Final Design Review Schedule, Thursday 18th and Friday 19th December:
|3:00pm||Arun Jayachandran, Bryson Kent, Samer Merchant, Jonathan Morgan|
|1:00pm||Bernard Chong, Jinpeng Lv, Kyung Jin Park, Xianzong Xie|
|1:30pm||Srinivas Chirla, Krishnaji Desai, Raghu Gudla|
|2:30pm||Chris Chadwick, Ahmed Ragab, Michael Stevens|
|3:00pm||Sandeep Chalasani, Abhishek Mathur, Sri Ramya Venumbaka|
|4:00pm||Shomit Das, Eliyah Kilada|
|4:30pm||Brandt Hammer, Ben Meakin, Robert Parry, Paul Pryor, Andrew Tolboe|