| Online Required Textbook: |
by Erik Brunvand
This is a required book for class this year.
Since it has not yet been published, Dr. Brunvand has made an online copy of it available to us on the web.
Please respect his copyright and only use this book for the course.
You will only be able to access this book from the University of Utah web site. If you are off-site you will need to log on using the Utah VPN Client on the web.
CONTENTS:
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Title page and table of contents | ||||||||
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Chapter 1: Getting Started | ||||||||
| Chapter 2: Cadence Design Framework | ||||||||
| Chapter 3: Composer Schematic Capture | ||||||||
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Chapter 4: Verilog Simulation | ||||||||
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Chapter 5: Virtuoso Layout Editor | ||||||||
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Chapter 6: Spectre Analog Simulation | ||||||||
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Chapter 7: Cell Characterization | ||||||||
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Chapter 8: Verilog Synthesis | ||||||||
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Chapter 9: Abstract Generation | ||||||||
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Chapter 10: SOC Encounter Place and Route | ||||||||
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Chapter 11: Chip Assembly |
Chapter 12: Design Example: TinyMIPS |
Appendix A: Tool Administration |
Appendix B: Highlights of the Tools |
Appendix C: Tool and Startup Scripts |
Appendix D: MOSIS SCMOS Rev8 Design Rules |
Appendix E: Technology and Cell Libraries |
Bibliography and Index | |